Silicon Valley

Computer chips tend to follow a standard design

Here’s a few highlights of a few days’ foraging in the USA, starting in Silicon Valley, California, where the surging creativity of new business formation is still in full swing, whatever the fears of the financial markets.

First stop was a behind-the-scenes computer company called Cadence. It designs and makes the machines that help companies in the hideously complex business of designing computer chips.

A talk with the Cadence CEO, Mike Fister, was one of the ways I wanted to explore the idea that Moore’s Law might soon run out of steam, and with it the ever-increasing pace of technology which has been a character of business and social life over the past 30 years.

Gordon Moore is one of the founders of the chip making giant Intel. His “law”, that the number of transistors on a chip doubles roughly every 24 months, has provided a roadmap for the hi-tech industry ever since he first came up with the observation in 1965.

But the lines that carry the tiny electric currents on the surface of the chip have been shrinking so repeatedly in response to Moore’s Law that they are now approaching the limits of some of the laws of physics. Maybe.

Crossing the line

Even as they go on shrinking, most chip designs still stick to the tried and tested grid system, called the Manhattan design.

Cadence has started designing chips where the lines go diagonally as well. The result (says Mike Fister) is considerably speedier computing.

Not everyone agrees, including the company where he worked for 20 years, Intel.

But is this reluctance to try out new designs an example of Moore’s Law becoming so vivid a prediction that it turns into a trap?

Driven by the Moore’s Law imperative, there seems to be little room for radical change from the ranks of suppliers who converge on a narrower line width every two years, with their ranks of million-dollar machines which do the complex work of chipmaking inside the fabrication plants owned by Intel, AMD and their rivals.

There’s little time for really new ideas when you are battling to master a new micron width technology.

One industry observer in Silicon Valley says: “They’re like polar bears on a melting iceberg.” The “bears” don’t agree. This was one theme of the trip.

Hello to hafnium

Everything is within a few miles of everything else in Silicon Valley – so it’s only a short trip next day to Intel’s HQ, which looks like every other Intel building in the world.

They’re “copied exactly” down to the doorknobs, a reminder to everyone who works there that copying chips onto silicon exactly is how the corporation makes its money.

But is it still silicon?

The question was posed by the highest placed Brit in Intel, Sean Maloney, whose job changes every time I see him – he’s currently chief sales and marketing officer.

Different techniques are being used in chip technology

He handed me a 300mm wafer made not of silicon, but on a new material including hafnium.

Silicon, with its insulating qualities, has been what computer chips have been etched on since they started.

But silicon is getting leaky and hot as the line widths shrink down to 45 microns, the width of a human hair.

So Intel has tuned to this new base, hafnium, to run cooler and less leaky chips, even though the activity on them is doubling in intensity all the time.

Those new chips aren’t on sale yet, but there’s a ferocious price war going on between Intel and its feisty but small rival, AMD. At the moment, AMD is losing out.

Meanwhile, IBM scientists report they’ve come up with a way of storing information on individual atoms, a deep dive into nanotechnology from the inventors of the scanning tunnelling microscope that makes it possible to “see” at these tiny levels.